An X-Band power amplifier design for on-chip RADAR applications

Tremendous growth of RAdio Detecting And Ranging (RADAR) and communication electronics require low manufacturing cost, excellent performance, minimum area and highly integrated solutions for transmitter/receiver (T/R) modules, which are one of the most important blocks of RADAR systems. New circuit topologies and process technologies are investigated to fulfill these requirements of next generation RADAR systems. With the recent improvements, Silicon-Germanium Bipolar CMOS technology became a good candidate for recently used III-V technologies, such as GaAs, InP, and GaN, to meet high speed and performance requirements of present RADAR applications. As new process technologies are used, new solutions and circuit architectures have to be provided while taking into account the advantages and disadvantageous of used technologies. In this thesis, a new T/R module system architecture is presented for single/onchip X-Band phased array RADAR applications. On-chip T/R module consists of five blocks; T/R switch, single-pole double-throw (SPDT) switch, low noise amplifier (LNA), power amplifier (PA), and phase shifter. As the main focus of this thesis, a two-stage power amplifier is realized, discussed and measured. Designed in IHP's 0.25 [micrometer] SiGe BiCMOS process technology, the power amplifier operates in Class-A mode to achieve high linearity and presents a measured small-signal gain of 25 dB at 10 GHz. While achieving an output power of 22 dBm, the power amplifier has drain efficiency of 30 % in saturation. The total die area is 1 [square millimeters], including RF and DC pads. To our knowledge, these results are comparable to and/or better than those reported in the literature

A new resonant circuit for 2.45 GHz LC VCO with linear frequency tuning

A new MOS varactor bank is proposed to implement a 2.45 GHz SiGe BiCMOS LC-tank voltage controlled oscillator (VCO) with linear frequency tuning. Compared to a conventional VCO, the proposed technique improves the quality factor of the LC-tank while preserving the linearity of the circuit. Realized in 0.25-μm SiGe BiCMOS technology, VCO exhibits 35% VCO gain (KVCO) variation from 2.29 to 2.66 GHz with a 16% tuning ratio. The VCO also exhibits a phase noise of -113 dBc/Hz at 1 MHz offset frequency and consumes 1.7 mA from 1.8 V supply

A high power handling capability CMOS T/R switch for x-band phased array antenna systems

This paper presents a single-pole double-throw (SPDT) transmit/receive (T/R) switch fabricated in 0.25-μm SiGe BiCMOS process for X-Band (8 – 12 GHz) phased array radar applications. The switch is based on series-shunt topology with combination of techniques to improve insertion loss (IL), isolation and power handling capability (P1dB). These techniques include optimization of transistor widths for lower insertion loss and parallel resonance technique to improve isolation. In addition, DC biasing of input and output ports, on-chip impedance transformation networks (ITN) and resistive body-floating are used to improve P1dB of the switch. All these design techniques resulted in a measured IL of 3.6 dB, isolation of 30.8 dB and P1dB of 28.2 dBm at 10 GHz. The return losses at both input and output ports are better than 16 dB from 8 to 12 GHz. To our knowledge, this work presents the highest P1dB at X-Band compared to other reported single-ended CMOS T/R switches in the literature

A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications

This paper presents a fractional N frequency synthesizer which covers WLAN and WiMAX frequencies on a single chip. The synthesizer is fully integrated in 0.35μm BiCMOS AMS technology except crystal oscillator. The synthesizer operates at four frequency bands (3.101-3.352GHz, 3.379-3.727GHz, 3.7-4.2GHz, 4.5-5.321GHz) to provide the specifications of 802.16 and 802.11 a/b/g/y. A single on-chip LC - Gm based VCO is implemented as the core of this synthesizer. Different frequency bands are selected via capacitance switching and fine tuning is done using varactor for each of these bands. A bandgap reference circuit is implemented inside of this charge pump block to generate temperature and power supply independent reference currents. Simulated settling time is around 10μsec. Total power consumption is measured to be 118.6mW without pad driving output buffers from a 3.3V supply. The phase noise of the oscillator is lower than -116.4dbc/Hz for all bands. The circuit occupies 2.784 mm2 on Si substrate, including DC, Digital and RF pads

Characterization of an embedded RF-MEMS switch

An RF-MEMS capacitive switch for mm-wave integrated circuits, embedded in the BEOL of 0.25μm BiCMOS process, has been characterized. First, a mechanical model based on Finite-Element-Method (FEM) was developed by taking the residual stress of the thin film membrane into account. The pull-in voltage and the capacitance values obtained with the mechanical model agree very well with the measured values. Moreover, S-parameters were extracted using Electromagnetic (EM) solver. The data observed in this way also agree well with the experimental ones measured up to 110GHz. The developed RF model was applied to a transmit/receive (T/R) antenna switch design. The results proved the feasibility of using the FEM model in circuit simulations for the development of RF-MEMS switch embedded, single-chip multi-band RF ICs

A new lab-on-chip transmitter for the detection of proteins using RNA aptamers

A new RNA aptamer based affinity biosensor for CReactive Protein (CRP), a risk marker for cardiovascular disease was developed using interdigitated capacitor (IDC), integrated in Voltage Controlled Oscillator (VCO) and output signal is amplified using Single Stage Power Amplifier (PA) for transmitting signal to receiver at Industrial, Scientific and Medical (ISM) band. The Lab-on-Chip transmitter design includes IDC, VCO and PA. The design was implemented in IHP 0.25μm SiGe BiCMOS process; post-CMOS process was utilized to increase the sensitivity of biosensor. The CRP was incubated between or on interdigitated electrodes and the changes in capacitance of IDC occurred. In blank measurements, the oscillation frequency was 2.464GHz whereas after RNA aptamers were immobilized on open aluminum areas of IDC and followed by binding reaction processed with 500pg/ml CRP solution, the capacitance shifted to 2.428GHz. Phase noise is changed from -114.3dBc/Hz to -116.5dBc/Hz

Single-Chip 64- and 256-Element Wafer-Scale Phased Arrays and Communication Circuits in Advanced SiGe and CMOS Technologies

The development of millimeter-wave phased arrays has been mostly based on silicon RFIC chips containing 8-16 channels and connected to antennas on organic printed circuit boards, or on wafer-scale phased arrays with on-chip antennas. Extending thewafer-scale array to a large number of elements results in an un-surmountable challenge, mainly that the phased-array chip may be much larger than a full reticle (approximately 22x22 mm2), and this is not allowed using standard integrated circuit design and layout rules. This dissertation focuses on the implementation of wafer-scale phased array with 64- and 256-elements using sub-reticle stitching techniques. An implementation of the largest single-chip wafer-scale phased-array ever built is demonstrated. The measured EIRP is 38 dBm and 45 dBm, with measured half-power beamwidth of 12.5 and 6 at 61 GHz for the 64- and 256-element phased arrays, respectively. This work allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together on a low cost board

Compact X-band SiGe power amplifier for single-chip phased array radar applications

An X-band power amplifier (PA) is presented for single-chip phased array radar applications. In this work, the choice of optimum circuit topology for X-band PA design is discussed and possible stability issues for high and low frequencies are analysed. The PA features a two-stage cascode architecture that includes both high-speed (low breakdown) and high breakdown (low-speed) SiGe transistors. It consists of two stages providing a 23.2 dBm saturated output power with a 28% power-added efficiency at 9 GHz. The output 1-dB compression point (P-1dB) is higher than 20 dBm in a 3 GHz bandwidth and has a maximum value of 22.2 dBm. The small-signal gain is 25.5 dB with a 3-dB bandwidth of 3.2 GHz (7.3-10.5 GHz). The PA has been fabricated using 0.25 mu m SiGe BiCMOS process provided by IHP Microelectronics. The PA occupies 1 mm x 0.6 mm chip area and consumes 120 mA from a 4 V supply voltage. These results demonstrate comparable or better performance than other reported PAs and suitable performance for single-chip phased array applications

CMOS SPDT T/R switch for X-band, on-chip radar applications

An SPDT transmit/receive (T/R) switch for X-band on-chip radar applications is proposed with the combination of new techniques. These methodologies include optimisation of the transistor widths for lower insertion loss (IL) while preserving high isolation and using a parallel resonance technique to improve isolation. Also, techniques such as applying DC bias to source and drain, using on-chip impedance transformation networks (ITN) and body-floating are used to improve power handling capability (P-1dB) of the switch. All these techniques result in the switch with insertion loss less than 1.3 dB, isolation between transmit and receive ports better than 29.2 dB, 29 dBm input P-1dB and return loss of better than 22 dB from 8 to 12 GHz in 0.44 mm(2) chip area